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5P49V5935 Datasheet(PDF) 14 Page - Integrated Device Technology

Part No. 5P49V5935
Description  Generates up to four independent output frequencies
Download  33 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5935 Datasheet(HTML) 14 Page - Integrated Device Technology

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PROGRAMMABLE CLOCK GENERATOR
14
REVISION B 07/13/15
5P49V5935 PRELIMINARY DATASHEET
Table 20:AC Timing Electrical Characteristics
(VDDO = 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol Parameter
Test Conditions
Min.
Typ.
Max.
Units
fIN 1
Input Frequency
Input frequency limit (CLKIN, CLKINB)
1350
MHz
Single ended clock output limit (LVCMOS)
1200
Differential cock output limit (LVPECL/ LVDS/HCSL)
1350
fVCO
VCO Frequency
VCO operating frequency range
2600
2800
3000
MHz
fPFD
PFD Frequency
PFD operating frequency range
1 1
150
MHz
fBW
Loop Bandwidth
Input frequency = 25MHz
0.06
0.9
MHz
t2
Input Duty Cycle
Duty Cycle
45
50
55
%
All differential outputs except Reference output
45
50
55
%
Measured at VDD/2, all outputs except Reference output 2.5V and 3.3V
45
50
55
%
Measured at VDD/2, all outputs except Reference output 1.8V
40
50
60
%
Measured at VDD/2, Reference output
(150.1MHz - 200MHz) with 50% input
40
50
60
%
Measured at VDD/2, Reference output(s)
(120.1MHz - 200MHz)
30
50
70
%
Slew Rate, SLEW[1:0] = 11
Single-ended 3.3V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
1.7
2.7
4.1
V/ns
Slew Rate, SLEW[1:0] = 10
Single-ended 3.3V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
1.4
2.4
3.8
V/ns
Slew Rate, SLEW[1:0] = 01
Single-ended 3.3V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
1.3
2.3
3.7
V/ns
Slew Rate, SLEW[1:0] = 00
Single-ended 3.3V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
1.1
2.1
3.6
V/ns
Slew Rate, SLEW[1:0] = 11
Single-ended 2.5V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.9
1.7
2.6
V/ns
Slew Rate, SLEW[1:0] = 10
Single-ended 2.5V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.6
1.4
2.3
V/ns
Slew Rate, SLEW[1:0] = 01
Single-ended 2.5V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.6
1.3
2.2
V/ns
Slew Rate, SLEW[1:0] = 00
Single-ended 2.5V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.6
1.2
2.1
V/ns
Slew Rate, SLEW[1:0] = 11
Single-ended 1.8V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.7
1.2
2.1
V/ns
Slew Rate, SLEW[1:0] = 10
Single-ended 1.8V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.4
0.9
1.7
V/ns
Slew Rate, SLEW[1:0] = 01
Single-ended 1.8V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.4
0.8
1.6
V/ns
Slew Rate, SLEW[1:0] = 00
Single-ended 1.8V LVCMOS output clock rise and fall time, @ 125MHz
25% to 75% of VDDO (Output Load = 5 pF)
0.3
0.7
1.4
V/ns
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
MHz
t5
ps
Output Duty Cycle
t4
fOUT
Output Frequency
t3 5


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