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5P49V5935 Datasheet(PDF) 26 Page - Integrated Device Technology

Part No. 5P49V5935
Description  Generates up to four independent output frequencies
Download  33 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5935 Datasheet(HTML) 26 Page - Integrated Device Technology

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PROGRAMMABLE CLOCK GENERATOR
26
REVISION B 07/13/15
5P49V5935 PRELIMINARY DATASHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs generate ECL/LVPECL compatible
outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality.
These outputs are designed to drive 50
 transmission lines.
Matched impedance techniques should be used to maximize
operating frequency and minimize signal distortion. The figure
below show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V LVPECL Output Termination (1)
3.3V LVPECL Output Termination (2)
LVPECL
Zo=50ohm
Zo=50ohm
3.3V
R1
R2
3.3V
50ohm
50ohm
RTT
50ohm
Input
+
-
LVPECL
Zo=50ohm
Zo=50ohm
3.3V
+
-
Input
R1
R2
3.3V
84ohm
84ohm
3.3V
R3
R4
125ohm
125ohm


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