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5P49V5925 Datasheet(PDF) 10 Page - Integrated Device Technology |
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5P49V5925 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 27 page  PROGRAMMABLE CLOCK GENERATOR 10 REVISION B 07/13/15 5P49V5925 DATASHEET I2C Mode Operation The device acts as a slave device on the I2C bus using one of the two I2C addresses (0xD0 or 0xD4) to allow multiple devices to be used in the system. The interface accepts byte-oriented block write and block read operations. Two address bytes specify the register address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the block write will be written simultaneously. For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-down resistors have a size of 100k typical. I2C Slave Read and Write Cycle Sequencing Current Read S Dev Addr + R A Data 0 A Data 1 A A Data n Abar P Sequential Read S Dev Addr + W A Data 0 A Data 1 A A Data n Abar P Reg start Addr A Sr Dev Addr + R A Sequential Write S Dev Addr + W A Data 0 P A Data 1 A A Data n A from master to slave from slave to master Reg start Addr A S = start Sr = repeated start A = acknowledge Abar= none acknowledge P = stop |
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