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5P49V5914 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. 5P49V5914
Description  Generates up to three independent output frequencies
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5914 Datasheet(HTML) 1 Page - Integrated Device Technology

 
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DATASHEET
5P49V5914 REVISION B 07/13/15
1
©2015 Integrated Device Technology, Inc.
Programmable Clock Generator
5P49V5914
Description
The 5P49V5914 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock.
The reference clock can come from one of the two redundant
clock inputs. A glitchless manual switchover function allows
one of the redundant clocks to be selected during normal
operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
Features
Generates up to three independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Three fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Three universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable slew rate control
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
1
7
24-pin VFQFPN
19
13
XOUT
XIN/REF
VDDO3
CLKIN
OUT3B
OUT2
CLKINB
CLKSEL
OUT3
OUT2B
VDDO2
VDDA
EPAD
GND
2
3
4
5
6
8
9 10 11 12
14
15
16
17
18
20
21
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