 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
5P49V5914 Datasheet(PDF) 5 Page - Integrated Device Technology |
|
||||||||||||||||||||||||||||||
5P49V5914 Datasheet(HTML) 5 Page - Integrated Device Technology |
|
|
5 / 37 page  REVISION B 07/13/15 5 PROGRAMMABLE CLOCK GENERATOR 5P49V5914 DATASHEET PLL Features and Descriptions Spread Spectrum To help reduce electromagnetic interference (EMI), the 5P49V5914 supports spread spectrum modulation. The output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system EMI. The 5P49V5914 implements spread spectrum using the Fractional-N output divide, to achieve controllable modulation rate and spreading magnitude. The Spread spectrum can be applied to any output clock, any clock frequency, and any spread amount from ±0.25% to ±2.5% center spread and -0.5% to -5% down spread. Table 2: Loop Filter PLL loop bandwidth range depends on the input reference frequency (Fref) and can be set between the loop bandwidth range as shown in the table below. Table 3: Configuration Table This table shows the SEL1, SEL0 settings to select the configuration stored in OTP. Four configurations can be stored in OTP. These can be factory programmed or user programmed. At power up time, the SEL0 and SEL1 pins must be tied to either the VDDD/VDDA power supply so that they ramp with that supply or are tied low (this is the same as floating the pins). This will cause the register configuration to be loaded that is selected according to Table 3 above. Providing that OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after the first 10mS of operation the levels of the SELx pins can be changed, either to low or to the same level as VDDD/VDDA. The SELx pins must be driven with a digital signal of < 300nS Rise/Fall time and only a single pin can be changed at a time. After a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. If OUT0_SEL_I2CB was 0 at POR, alternate configurations can only be loaded via the I2C interface. Table 4: Input Clock Select Input clock select. Selects the active input reference source in manual switchover mode. 0 = XIN/REF, XOUT (default) 1 = CLKIN, CLKINB CLKSEL Polarity can be changed by I2C programming as shown in Table 4. PRIMSRC is bit 1 of Register 0x13. Input Reference Frequency–Fref (MHz) Loop Bandwidth Min (kHz) Loop Bandwidth Max (kHz) 540 126 350 300 1000 OUT0_SEL_I2CB @ POR SEL1 SEL0 I2C Access REG0:7 Config 10 0 No 0 0 10 1 No 0 1 11 0 No 0 2 11 1 No 0 3 0 X X Yes 1 I2C defaults 0X X Yes 0 0 PRIMSRC CLKSEL Source 0 0 XIN/REF 0 1 CLKIN, CLKINB 1 0 CLKIN, CLKINB 1 1 XIN/REF |
Similar Part No. - 5P49V5914 |
|
Similar Description - 5P49V5914 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
