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5P49V5914 Datasheet(PDF) 26 Page - Integrated Device Technology |
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5P49V5914 Datasheet(HTML) 26 Page - Integrated Device Technology |
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PROGRAMMABLE CLOCK GENERATOR 26 REVISION B 07/13/15 5P49V5914 DATASHEET CLKIN Equivalent Schematic Wiring the Differential Input to Accept Single-Ended Levels Figure Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels shows how a differential input can be wired to accept single ended levels. This configuration has three properties; the total output impedance of Ro and Rs matches the 50 ohm transmission line impedance, the Vrx voltage is generated at the CLKIN inputs which maintains the LVCMOS driver voltage level across the transmission line for best S/N and the R1-R2 voltage divider values ensure that Vrx p-p at CLKIN is less than the maximum value of 1.2V. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels R1 R2 Vrx Vers aClock 5 Receiver CLKI N CLKI NB LVCMOS VDD Zo = 50 Ohm Ro + Rs = 5 0 Rs Ro |
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