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5P49V5914 Datasheet(PDF) 25 Page - Integrated Device Technology

Part No. 5P49V5914
Description  Generates up to three independent output frequencies
Download  37 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5914 Datasheet(HTML) 25 Page - Integrated Device Technology

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REVISION B 07/13/15
25
PROGRAMMABLE CLOCK GENERATOR
5P49V5914 DATASHEET
LVPECL Driver
Figure General Diagram for LVPECL Driver to XTAL Input
Interface shows an example of the interface diagram for a
+3.3V LVPECL driver. This is a standard LVPECL termination
with one side of the driver feeding the XIN/REF input. It is
recommended that all components in the schematics be
placed in the layout; though some components might not be
used, they can be utilized for debugging purposes. The
datasheet specifications are characterized and guaranteed by
using a quartz crystal as the input. If the driver is 2.5V
LVPECL, the only change necessary is to use the appropriate
value of R3.
General Diagram for +3.3V LVPECL Driver to XTAL Input Interface
CLKIN Equivalent Schematic
Figure CLKIN Equivalent Schematic below shows the basis of
the requirements on VIH max, VIL min and the 1200 mV p-p
single ended Vswing maximum.
The CLKIN and CLKINB Vih max spec comes from the
cathode voltage on the input ESD diodes D2 and D4, which
are referenced to the internal 1.2V supply. CLKIN or
CLKINB voltages greater than 1.2V + 0.5V =1.7V will be
clamped by these diodes. CLKIN and CLKINB input
voltages less than -0.3V will be clamped by diodes D1 and
D3.
The 1.2V p-p maximum Vswing input requirement is
determined by the internally regulated 1.2V supply for the
actual clock receiver. This is the basis of the Vswing spec in
Table 13.
 
+3.3V LVPECL Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
R2
50
R3
50
XOUT
XIN / REF
C1
0. 1 uF


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