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5P49V5914 Datasheet(PDF) 18 Page - Integrated Device Technology

Part No. 5P49V5914
Description  Generates up to three independent output frequencies
Download  37 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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5P49V5914 Datasheet(HTML) 18 Page - Integrated Device Technology

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PROGRAMMABLE CLOCK GENERATOR
18
REVISION B 07/13/15
5P49V5914 DATASHEET
Table 21:1AC Timing Electrical Characteristics
(VDDO = 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Input frequency limit (XIN)
840
MHz
Input frequency limit (REF)
1200
MHz
Input frequency limit (CLKIN, CLKINB)
1350
MHz
Single ended clock output limit (LVCMOS)
1200
Differential clock output limit (LVPECL/
LVDS/HCSL)
1350
fVCO
VCO Frequency
VCO operating frequency range
2800
MHz
fPFD
PFD Frequency
PFD operating frequency range
0.8 1
100
MHz
fBW
Loop Bandwidth
Input frequency = 25MHz
0.08
0.5
MHz
t2
Input Duty Cycle
Duty Cycle
45
55
%
All differential outputs except Reference
output
45
50
55
%
Measured at VDD/2, all outputs except
Reference output 2.5V and 3.3V
45
50
55
%
Measured at VDD/2, all outputs except
Reference output 1.8V
40
50
60
%
Measured at VDD/2, Reference output
(150.1MHz - 200MHz) with 50% input
40
50
60
%
Measured at VDD/2, Reference output(s)
(120.1MHz - 200MHz)
30
50
70
%
Slew Rate, SLEW[1:0] = 00
1.5
2.6
4.0
Slew Rate, SLEW[1:0] = 01
1.3
2.4
3.8
Slew Rate, SLEW[1:0] = 10
1.2
2.3
3.7
Slew Rate, SLEW[1:0] = 11
1.0
2.2
3.6
Slew Rate, SLEW[1:0] = 00
1.0
1.7
2.7
Slew Rate, SLEW[1:0] = 01
0.8
1.5
2.5
Slew Rate, SLEW[1:0] = 10
0.7
1.4
2.45
Slew Rate, SLEW[1:0] = 11
0.6
1.3
2.39
Slew Rate, SLEW[1:0] = 00
1.5
2.6
4.0
Slew Rate, SLEW[1:0] = 01
1.3
2.4
3.8
Slew Rate, SLEW[1:0] = 10
1.2
2.3
3.75
Slew Rate, SLEW[1:0] = 11
1.0
2.2
3.67
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=2.5V
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=1.8V
fOUT
Output Frequency
MHz
t5
ps
t4 2
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDD=3.3V
V/ns
fIN 1
Input Frequency
t3 5
Output Duty Cycle


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