Rev C 3/23/15

7

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

87016I DATA SHEET

All parameters measured at 250MHz unless noted otherwise.

NOTE 2: Defined as skew within a bank with equal load conditions.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using

NOTE 5: These parameters are guaranteed by characterization. Not tested in production.

NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

For NOTES, please see above, Table 5C.

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

250

MHz

Propagation

Delay,

Low to High

CLK0;

NOTE 1A

2.9

3.5

4.0

ns

CLK1/CLK1;

NOTE 1B

3.0

3.5

4.0

ns

tsk(b)

Bank Skew; NOTE 2, 6

Measured on the Rising Edge

50

ps

tsk(o)

Output Skew; NOTE 3, 6

Measured on the Rising Edge

170

ps

tsk(pp)

Part-to-Part Skew; NOTE 4, 6

800

ps

Output Rise/Fall Time; NOTE 5

20% to 80%

200

700

ps

odc

Output Duty Cycle

ƒ< 175MHz

45

55

%

ƒ

 175MHz

40

60

%

Output Enable Time; NOTE 5

10

ns

Output Disable Time; NOTE 5

10

ns

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Output Frequency

250

MHz

Propagation

Delay,

Low to High

CLK0;

NOTE 1A

3.0

3.9

4.7

ns

CLK1/CLK1;

NOTE 1B

3.0

3.9

4.7

ns

tsk(b)

Bank Skew; NOTE 2, 6

Measured on the Rising Edge

50

ps

tsk(o)

Output Skew; NOTE 3, 6

Measured on the Rising Edge

170

ps

tsk(pp)

Part-to-Part Skew; NOTE 4, 6

800

ps

Output Rise/Fall Time; NOTE 5

20% to 80%

200

700

ps

odc

Output Duty Cycle

ƒ< 175MHz

45

55

%

ƒ

 175MHz

40

60

%

Output Enable Time; NOTE 5

10

ns

Output Disable Time; NOTE 5

10

ns