STC5425 datasheet(6/48 Pages) CONNOR-WINFIELD

Part #	STC5425

Description	Line Card Clock

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Manufacturer	CONNOR-WINFIELD [Connor-Winfield Corporation]

Direct Link	http://www.conwin.com

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Page 6 of 48

TM113

Rev:P1.3

Date: September 20, 2011

STC5425

Line Card Clock

Data sheet

Preliminary

STC5425 Pin Description

All I/O is LVCMOS, except for CLK1 is LVPECL/LVDS. REF4 and REF5 are LVCMOS/LVPECL/LVDS.

Table 1: Pin Description

Pin Name

Pin #

I/O

Description

AVCC

4,14

3.3V analog power input

AGND

3,15

Analog ground

VCC

8, 9, 12,

22, 32,

36, 38,

39, 45,

46, 54,

57

3.3V digital power input

GND

1, 7, 10,

11, 21,

31, 40,

53, 58

Digital ground

TRST

37

I

JTAG boundary scan reset, active low

TCK

49

I

JTAG boundary scan clock

TMS

41

I

JTAG boundary scan mode selection

TDI

51

I

JTAG boundary scan data input

TDO

50

O

JTAG boundary scan data output

RST

48

I

Active low to reset the chip

MCLK

6

I

Master clock input (TCXO or XO)

EVENT_INTR

5

O

Event interrupt

EX_SYNC1

28

I

Frame Sync signal 1

EX_SYNC2

33

I

Frame Sync signal 2

EX_SYNC3

35

I

Frame Sync signal 3

REF1

29

I

Reference input 1

REF2

30

I

Reference input 2

REF3

34

I

Reference input 3

REF4_P

23

I

Differential reference input 4 (LVPECL/LVDS)

REF4_N

24

I

Differential reference input 4 (LVPECL/LVDS)

REF5_P

25

I

Differential reference input 5 (LVPECL/LVDS)

REF5_N

26

I

Differential reference input 5 (LVPECL/LVDS)

CLK1_P

19

O

Clock output CLK1 positive. 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK1_N

20

O

Clock output CLK1 negative, 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G1

LVPECL or LVDS

CLK2

56

O

Clock output CLK2 1MHz to 156.25MHz, in 1kHz steps, from Synthesizer G3, proprietary

composite signal of Synthesizer F or Synthesizer GT4 (T4). LVCMOS.

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