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9ZXL1231 Datasheet(PDF) 2 Page - Integrated Device Technology |
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9ZXL1231 Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 18 page DB1200ZL 12-OUTPUT LOW POWER HCSL BUFFER 2 REVISION F 07/14/15 9ZXL1231 DATASHEET Pin Configuration Power Management Table Functionality at Power-up (PLL mode) Power Connections 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDA 148 GND GNDA 247 DIF_7# NC 346 DIF_7 100M_133M# 445 vOE7# HIBW_BYPM_LOBW# 544 vOE6# CKPWRGD_PD# 643 DIF_6# GND 742 DIF_6 VDDR 841 GND DIF_IN 940 VDD DIF_IN# 10 39 DIF_5# SMB_A0_tri 11 38 DIF_5 SMBDAT 12 37 vOE5# SMBCLK 13 36 vOE4# SMB_A1_tri 14 35 DIF_4# DFB_OUT_NC# 15 34 DIF_4 DFB_OUT_NC 16 33 GND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Note: Pins with ^ prefix have internal 120K pullup Pins with v prefix have internal 120K pulldowm 9ZXL1231 connect epad to ground 9x9mm 64-pin VFQFPN CKPWR GD_PD# DIF_IN/ DIF_IN# SMBus EN bit DIF(11:0)/ DIF(11:0)# PLL STATE IF NOT IN BYPASS MODE 0X X Low/Low OFF 0Low/Low ON 1Running ON Running 1 100M_133M# DIF_IN MHz DIF(11:0) 1 100.00 DIF_IN 0 133.33 DIF_IN VDD VDDIO GND 12 Analog PLL 8 7 Analog Input 24,40,57 25,32,49,56 23,33,41,48,58 DIF clocks Pin Number Description |
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