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9FGV0431 Datasheet(PDF) 14 Page - Integrated Device Technology |
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9FGV0431 Datasheet(HTML) 14 Page - Integrated Device Technology |
14 / 15 page 9FGV0431 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR IDT® 4-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR 14 9FGV0431 REV D 022613 Revision History Rev. Issue Date Intiator Description Page # A 8/14/2012 RDW 1. Changed Description, Recommended Application and DS title to say "Clock Generator" instead of "Frequency Generator" 2. Changed Output Features text. 3. Highlighted the standby power pins in the pinout (pins 4,5,8) 4. Added footnote 1 to Power Management Table 3. Cleaned up the Test Load Diagrams and merged with Alternate Terminations Diagram, added missing REF diagram. 4. Updated electrical tables with char data, removed "Clock Periods-Single- ended Outputs" table which was redundant. Updated footnote two on Clock Periods Table. 5. Changed integration range for phase jitter calculation of REF from "12kHz to 20MHz" to "12kHz to 5MHz" 6. Corrected Byte 6 7. Added Thermal Data and Recommended Crystal tables 8. Move to final. 1,2,4,5- 8,11-13 B 10/3/2012 RDW Pin description for pin named "VDDREF1.8" is unclear due to typographical error. The pin description for pin with this name is currently, VDD for REF output. 1.8V nominal 3.3V. The correct description should be "VDD for REF output. nominal 1.8V." 3 C 12/20/2012 AT Changed VIH min. from 0.65*VDD to 0.75*VDD, VIM min. from 0.35*VDD to 0.4*VDD and max. from 0.65*VDD to 0.6*VDD, and VIL max. from 0.35*VDD to 0.25*VDD 6 D 1/21/2013 RDW Minor adjustments to electrical tables as follows: 1. DIF output slew rate limits adjusted from 2~4 and 1~3 V/ns to 2.6~4.6 and 1.5~3.5V/ns. 2. REF duty cycle and duty cycle distortion values were swapped and are corrected. 3. Typical values of many parameters slightly adjusted. 5-8 D 2/26/2013 RDW Corrected typo in industrial temp rating in ordering information; added "-" to 40. 13 |
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