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9DBV0441 Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part # 9DBV0441
Description  53mW typical power consumption in PLL mode
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

9DBV0441 Datasheet(HTML) 8 Page - Integrated Circuit Systems

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4 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHM
8
REVISION D 11/26/14
9DBV0441 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Scope averaging on 3.0V/ns setting
1.1
2
3
V/ns
1, 2, 3
Scope averaging on 2.0V/ns setting
1.9
3
4
V/ns
1, 2, 3
Slew rate matching
ΔTrf
Slew rate matching, Scope averaging on
7
20
%
1, 2, 4
Voltage High
VHIGH
660
774
850
1,7
Voltage Low
VLOW
-150
18
150
1,7
Max Voltage
Vmax
821
1150
1
Min VoltageVmin
-300
-15
1
Vswing
Vswing
Scope averaging off
300
1536
mV
1,2,7
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
414
550
mV
1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
13
140
mV
1, 6
2 Measured from differential waveform
Slew rate
Trf
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1Guaranteed by design and characterization, not 100% tested in production.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
IDDAOP
VDDA+VDDR, PLL Mode, @100MHz
11
15
mA
1
IDDOP
VDD1.8, All outputs active @100MHz
25
35
mA
1
IDDAPD
VDDA+VDDR, PLL Mode, @100MHz
1
mA
1,2
IDDPD
VDD1.8, Outputs Low/Low
1.2
mA
1, 2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
Operating Supply Current
Powerdown Current


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