Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

9DBU0731 Datasheet(PDF) 8 Page - Integrated Circuit Systems

Part No. 9DBU0731
Description  slew rate for each output
Download  17 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

9DBU0731 Datasheet(HTML) 8 Page - Integrated Circuit Systems

Back Button 9DBU0731 Datasheet HTML 4Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 5Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 6Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 7Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 8Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 9Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 10Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 11Page - Integrated Circuit Systems 9DBU0731 Datasheet HTML 12Page - Integrated Circuit Systems Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 17 page
background image
7 O/P 1.5V PCIE GEN1-2-3 FAN-OUT BUFFER
8
REVISION C 04/22/15
9DBU0731 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Duty Cycle Distortion
tDCD
Measured differentially, @100MHz
-1
-0.2
0.5
%
1,3
Skew, Input to Output
tpdBYP
Bypass Mode, VT = 50%
2400
2862
3700
ps
1
Skew, Output to Output
tsk3
VT = 50%
30
60
ps
1,4
Jitter, Cycle to cycle
tjcyc-cyc
Additive Jitter in Bypass Mode
0.1
5
ps
1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
INDUSTRY
LIMIT
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
0.1
5
N/A
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1
0.4
N/A
ps
(rms)
1,2,3,4,
5
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1
0.7
N/A
ps
(rms)
1,2,3,4
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.3
N/A
ps
(rms)
1,2,3,4
tjphSGMIIM0
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff >
10MHz
200
250
N/A
fs
(rms)
1,6
tjphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff >
10MHz
313
350
N/A
fs
(rms)
1,6
1Guaranteed by design and characterization, not 100% tested in production.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FGV0831 or equivalent
6 Rohde&Schwarz SMA100
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Additive Phase Jitter,
Bypass Mode
tjphPCIeG2


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn