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9DB433 Datasheet(PDF) 3 Page - Integrated Circuit Systems

Part # 9DB433
Description  SMBus Interface; unused outputs can be disabled
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

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9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
3
9DB433
REV G 08/25/15
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDDR
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4
GND
PWR
Ground pin.
5
VDD
PWR
Power supply, nominal 3.3V
6
DIF_1
OUT
0.7V differential true clock output
7
DIF_1#
OUT
0.7V differential Complementary clock output
8OE1#
IN
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
9
DIF_2
OUT
0.7V differential true clock output
10
DIF_2#
OUT
0.7V differential Complementary clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
BYP#_HIBW_LOBW
IN
Tri-level input to select bypass mode, Hi BW PLL, or Lo BW PLL mode
13
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
14
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
15
GND
PWR
Ground pin.
16
VDD
PWR
Power supply, nominal 3.3V
17
SMB_ADR_tri
IN
SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus
Addresses.
18
VDD
PWR
Power supply, nominal 3.3V
19
DIF_5#
OUT
0.7V differential Complementary clock output
20
DIF_5
OUT
0.7V differential true clock output
21
OE6#
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
22
DIF_6#
OUT
0.7V differential Complementary clock output
23
DIF_6
OUT
0.7V differential true clock output
24
VDD
PWR
Power supply, nominal 3.3V
25
PD#
IN
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
26
IREF
OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See data
sheet.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.


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