Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

MAX3761 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part No. MAX3761
Description  Low-Power, 622Mbps Limiting Amplifiers with Chatter-Free Power Detect for LANs
Download  12 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
Logo 

MAX3761 Datasheet(HTML) 6 Page - Maxim Integrated Products

Zoom Inzoom in Zoom Outzoom out
 6 / 12 page
background image
Low-Power, 622Mbps Limiting Amplifiers
with Chatter-Free Power Detect for LANs
6
_______________________________________________________________________________________
_______________Detailed Description
Figure 1 shows the functional diagram for the MAX3761/
MAX3762. The input signal is applied to VIN+ and VIN-.
A chain of amplifier stages, each contributing approxi-
mately 12.5dB of gain, amplifies the input signal to
PECL output voltage swings. A 4mVp-p input signal will
cause the output to fully limit.
Received-Signal-Strength
Indicator (RSSI)
Each amplifier stage contains a full-wave logarithmic
detector (FWD). The full-wave detector outputs are
summed at the FILTER pin and used to generate the
received-signal-strength indication (RSSI). The RSSI
output voltage is linearly proportional to the input power
(in decibels), and is approximated by:
where VIN is the peak-to-peak input signal in millivolts.
The RSSI output is insensitive to fluctuations in temperature
and supply voltage. The power detector functions as a
broadband power meter that detects the total power of all
signals present in the passband of approximately 750MHz.
Refer to the Typical Operating Characteristics graphs show-
ing RSSI output versus input power and signal amplitude.
The high-speed RSSI signal is filtered with one external
capacitor connected from FILTER to VCC. The imped-
ance at the FILTER pin is approximately 500
Ω.
The FILTER capacitor (CFILTER) must be connected
to VCC for proper operation.
Input-Offset Correction
The limiting amplifier provides approximately 60dB of
gain. An input DC offset of even 1mV reduces the
power-detection circuit’s accuracy and can cause the
output to limit. A low-frequency feedback loop is inte-
grated into the MAX3761/MAX3762 to remove input off-
set. DC coupling the inputs is not recommended, as
this prevents the DC-offset-correction circuitry from
functioning properly. Input offset is typically reduced to
less than 100µV.
The capacitance between pins CZP and CZN, in parallel
with a 10pF integrated capacitance, determines the off-
set-correction circuit’s time constant. The input imped-
ance between CZP and CZN is approximately 800k
Ω.
The offset correction circuitry requires an average data-
input duty cycle of 50%. If the input data has a different
average duty cycle, the output will have increased
pulse-width distortion.
V
(V) = 1.13 + 0.457log (V )
RSSI
IN
LIMITER
FWD
LIMITER
FWD
LIMITER
FWD
FILTER
REF
INV
VTH
R1
R2
GNDO
LOS+/LOS-
VCC - 2V
RSSI
50
OUT+/OUT-
DISABLE
VCCO
EN
CZN
CAZ
CZP
SUB
GND
VCC
VIN+/VIN-
CIN
CFILTER
VCC
FWD = FULL-WAVE DETECTOR
LIMITER
FWD
MAX3761/MAX3762
Figure 1. Functional Diagram


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn