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MAX3675 Datasheet(PDF) 13 Page - Maxim Integrated Products

Part No. MAX3675
Description  622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX3675 Datasheet(HTML) 13 Page - Maxim Integrated Products

 
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622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
______________________________________________________________________________________
13
allowable pattern-dependent jitter, peak-to-peak
(seconds); and BW = typical system bandwidth, nor-
mally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is
still larger than desired, continue increasing the value of
CIN. Note that to maintain stability when using the
MAX3675 analog inputs (ADI+, ADI-), it is important to
keep the low-frequency cutoff associated with COLC
below the corner frequency associated with CIN (fC)
(Table 1).
PDJ can also be present due to insufficient high-fre-
quency bandwidth (Figure 10). If the amplifiers are not
fast enough to allow for complete transitions during sin-
gle-bit patterns, or if the amplifier does not allow ade-
quate settling time, high-frequency PDJ can result.
Pulse-Width Distortion (PWD)
Finally, PWD occurs when the midpoint crossing of a
0–1 transition and a 1–0 transition do not occur at the
same level (Figure 11). DC offsets and nonsymmetrical
rising and falling edge speeds both contribute to PWD.
For a 1–0 bit stream, calculate PWD as follows:
PWD = [(width of wider pulse) -
(width of narrower pulse)] / 2
Phase Adjust
The internal clock and data alignment in the MAX3675
is well maintained close to the center of the data eye.
Although not required, this sampling point can be shift-
ed using the PHADJ inputs to optimize BER perfor-
mance. The PHADJ inputs operate with differential
input signals to approximately ±1V. A simple resistor
divider with a bypass capacitor is sufficient to set up
these levels. When the PHADJ inputs are not used, they
should be tied directly to VCC.
Figure 10. Pattern-Dependent Jitter Due to High-Frequency
Rolloff
TIME
MIDPOINT
LONG
CONSECUTIVE
BIT STREAM
0-1-0 BIT STREAM
HF PDJ
Figure 11. Pulse-Width Distortion
TIME
MIDPOINT
WIDTH OF A ONE
WIDTH OF A ZERO
PWD RESULTS WHEN THE WIDTH
OF A ZERO DOES NOT EQUAL
THE WIDTH OF A ONE
tFALL ≠ tRISE


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