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MAX3675 Datasheet(PDF) 8 Page - Maxim Integrated Products

Part No. MAX3675
Description  622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
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Maker  MAXIM [Maxim Integrated Products]
Homepage  http://www.maxim-ic.com
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MAX3675 Datasheet(HTML) 8 Page - Maxim Integrated Products

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622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier
8
_______________________________________________________________________________________
Phase Detector
The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov-
ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.
Frequency Detector
A frequency detector incorporated into the PLL aids
frequency acquisition during start-up conditions. The
input data stream is sampled by quadrature compo-
nents of the VCO clock, generating a difference fre-
quency. Depending on the polarity of the difference
frequency, the PFD drives the VCO so that the differ-
ence frequency is reduced to zero. Once frequency
acquisition is obtained, the frequency detector returns
to a neutral state.
Loop Filter and VCO
The VCO is fully integrated, while the loop filter requires
an external R-C network. This filter network determines
the bandwidth and peaking of the second-order PLL.
__________________Design Procedure
Received-Signal-Strength
Indicator (RSSI)
The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVp-p to 50mVp-p.
The slope over this input range is approximately
29mV/dB.
The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to VCC. The
impedance looking into CFILT is about 500
Ω to VCC. As
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:
For 622Mbps applications, Maxim recommends a cut-
off frequency of 6.8kHz, which requires CF = 47nF. The
RSSI output is designed to drive a minimum load resis-
tance of 10k
Ω to ground and a maximum of 20pF.
Loads greater than 20pF must be buffered by a series
resistance of 10k
Ω (i.e., voltmeter).
Input Offset Correction
The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated
into the MAX3675 to remove the input offset. DC cou-
pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset-
correction circuitry.
The differential input impedance (ZIN) is approximately
2.5k
Ω. The impedance between OLC+ and OLC- (ZOLC)
is approximately 120k
Ω. Take care when setting the
combined low-frequency cutoff (fCUTOFF), due to the
input DC-blocking capacitor (CIN) and the offset correc-
tion loop capacitor (COLC). Refer to Table 1 for selecting
the values of CIN and COLC.
These values ensure that the poles associated with CIN
and COLC work together to provide a flat response at the
lower -3dB corner frequency (no gain peaking).
CIN must be a low-TC, high-quality capacitor of type X7R
or better in order to minimize fCUTOFF deviations. COLC
must be a capacitor of type Z5U or better.
Loss-of-Power (LOP) Monitor
A LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (VTH), which is set exter-
nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.18V), is supplied for programming
a supply-independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. VTH is programmable from 1.18V to 2.4V using
the equation:
The op amp can source only 20µA of current.
Therefore, an R1 value greater than or equal to 100k
is recommended for proper operation. The input bias
V
= 1.18 1 + R2 / R1
TH
()
f
= 1 / 2 500
FILT
π
()
[]
CF
COLC
COMBINED LOW
fCUTOFF (kHz)
2200pF
4700pF
29
1000pF
3300pF
68
CIN
470pF
1000pF
135
330pF
680pF
190
220pF
470pF
290
Table 1. Setting the Low-Frequency Cutoff
4700pF
0.010µF
13.5
6800pF
0.022µF
10
0.010µF
0.033µF
6.8
0.022µF
0.047µF
3.0


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