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IR3551 Datasheet(PDF) 4 Page - International Rectifier
IRF [International Rectifier]
IR3551 Datasheet(HTML) 4 Page - International Rectifier
/ 22 page
July 16, 2013 | DATASHEET V3.2
50A Integrated PowIRstage®
Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.
Non-Inverting input to the current sense amplifier. Connect to LGND if the current sense
amplifier is not used.
Bias voltage for control logic. Connect a minimum 1uF cap between VCC and PGND (pin
4) if current sense amplifier is used. Connect a minimum 0.22uF capacitor between VCC
and PGND (pin 4) if current sense amplifier is not used.
4, 14, 15
Power ground of MOSFET driver and the synchronous MOSFET. MOSFET driver signal is
referenced to this pin.
Low-side MOSFET driver pins that can be connected to a test point in order to observe
6 – 13
Switch node of synchronous buck converter.
16 – 19
High current input voltage connection. Recommended operating range is 4.5V to 15V.
Connect at least two 10uF 1206 ceramic capacitors and a 0.22uF 0402 ceramic
capacitor. Place the capacitors as close as possible to VIN pins and PGND pins (14-15).
The 0.22uF 0402 capacitor should be on the same side of the PCB as the IR3551.
Bootstrap capacitor connection. The bootstrap capacitor provides the charge to turn on
the control MOSFET. Connect a minimum 0.22µF capacitor from BOOST to SW pin. Place
the capacitor as close to BOOST pin as possible and minimize parasitic inductance of
PCB routing from the capacitor to SW pin.
Open drain output of the phase fault circuits. Connect to an external pull-up resistor.
Output is low when a MOSFET fault or over temperature condition is detected.
3.3V logic level tri-state PWM input and 7V tolerant. “High” turns the control MOSFET
on, and “Low” turns the synchronous MOSFET on. “Tri-state” turns both MOSFETs off in
Body-Braking® mode. In diode emulation mode, “Tri-state” activates internal diode
emulation control. See “PWM Tri-state Input” Section for further details about the PWM
3.3V logic level input and 7V tolerant with internal weak pull-up to 3.3V. Logic low
disables both MOSFETs. Pull up to VCC directly or by a 4.7kΩ resistor if Body-Braking® is
not used. The second function of the BBRK# pin is to select diode emulatiom mode.
Pulling BBRK# low at least 20ns after VCC passes its UVLO threshold selects internal
diode emulation control. See “Body-Braking® Mode” Section for further details.
Signal ground. Driver control logic, analog circuits and IC substrate are referenced to
Reference voltage input from the PWM controller. IOUT signal is referenced to the
voltage on this pin. Connect to LGND if the current sense amplifier is not used.
Current output signal. Voltage on this pin is equal to V(REFIN) + 32.5 * [V(CSIN+) –
V(CSIN-)]. Float this pin if the current sense amplifier is not used.
This pin is connected to internal power and signal ground of the driver. For best
performance of the current sense amplifier, TGND must be electrically isolated from
Power Ground (PGND) and Signal Ground (LGND) in the PCB layout. Connect to PGND if
the current sense amplifier is not used.
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