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74AUP1G132 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G132 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74AUP1G132 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 — 29 June 2012 3 of 22 NXP Semiconductors 74AUP1G132 Low-power 2-input NAND Schmitt trigger 7. Pinning information 7.1 Pinning 7.2 Pin description Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886 74AUP1G132 BVCC A GND Y 001aac531 1 2 3 5 4 74AUP1G132 A 001aac530 B GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 74AUP1G132 A 001aaf508 B GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 B VCC GND 1 3 2 5 4 A Y aaa-003012 Transparent top view 74AUP1G132 Table 3. Pin description Symbol Pin Description TSSOP5 and X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage |
Similar Part No. - 74AUP1G132_15 |
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Similar Description - 74AUP1G132_15 |
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