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PEX8733 Datasheet(PDF) 3 Page - AVAGO TECHNOLOGIES LIMITED

Part No. PEX8733
Description  PCI Express Gen 3 Switch
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Maker  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Homepage  http://www.avagotech.com
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PEX8733 Datasheet(HTML) 3 Page - AVAGO TECHNOLOGIES LIMITED

   
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PEX8733, PCI Express Gen 3 Switch, 32 Lanes, 18 Ports
© PLX Technology, www.plxtech.com
Page 3 of 5
22Aug11, version 1.0
and r1.0a. Additionally, it supports auto-negotiation, lane
reversal, and polarity reversal. Furthermore, the
PEX8733 is tested for Microsoft Vista compliance as well.
All PLX switches undergo thorough interoperability
testing in PLX’s Interoperability Lab and compliance
testing at the PCI-SIG plug-fest.
performancePAK
Exclusive to PLX, performancePAK is a suite of unique
and innovative performance features which allows PLX’s
Gen 3 switches to be the highest performing Gen 3
switches in the market today. The performancePAK
features consists of the Read Pacing, Multicast, and
Dynamic Buffer Pool.
Read Pacing
The Read Pacing feature allows users to throttle the
amount of read requests being made by downstream
devices. When a downstream device requests several long
reads back-to-back, the Root Complex gets tied up in
serving that downstream port. If that port has a narrow link
and is therefore slow in receiving these read packets from
the Root Complex, then other downstream ports may
become starved – thus, impacting performance. The Read
Pacing feature enhances performances by allowing for the
adequate servicing of all downstream devices.
Multicast
The Multicast feature enables the copying of data (packets)
from one ingress port to multiple (up to 17) egress ports in
one transaction allowing for higher performance in dual-
graphics, storage, security, and redundant applications,
among others. Multicast relieves the CPU from having to
conduct multiple redundant transactions, resulting in
higher system performance.
Dynamic Buffer Pool
The PEX8733 employs a dynamic buffer pool for Flow
Control (FC) management. As opposed to a static buffer
scheme which assigns fixed, static buffers to each port,
PLX’s dynamic buffer allocation scheme utilizes a
common pool of FC Credits which are shared by other
ports. This shared buffer pool is fully programmable by the
user, so FC credits can be allocated among the ports as
needed. Not only does this prevent wasted buffers and
inappropriate buffer assignments, any unallocated buffers
remain in the common buffer pool and can then be used
for faster FC credit updates.
visionPAK
Another PLX exclusive, visionPAK is a debug diagnostics
suite of integrated hardware and software instruments that
users can use to help bring their systems to market faster.
visionPAK features consist of Performance Monitoring,
SerDes Eye Capture, Error Injection, SerDes Loopback,
and more.
Performance Monitoring
The PEX8733’s real time performance monitoring allows
users to literally “see” ingress and egress performance on
each port as traffic passes through the switch using PLX’s
Software Development Kit (SDK). The monitoring is
completely passive and therefore has no affect on overall
system performance. Internal counters provide extensive
granularity down to traffic & packet type and even allows
for the filtering of traffic (i.e. count only Memory Writes).
SerDes Eye Capture
Users can evaluate their system’s signal integrity at the
physical layer using the PEX8733’s SerDes Eye Capture
feature. Using PLX’s SDK, users can view the receiver
eye of any lane on the switch. Users can then modify
SerDes settings and see the impact on the receiver eye.
Figure 5 shows a screenshot of the SerDes Eye Capture
feature in the SDK.
Figure 5. SerDes Eye Capture
PCIe Packet Generator
The PEX8733 features a full-fledged PCIe Packet
Generator capable of creating programmable PCIe traffic
running at up to Gen 3 speeds and capable of saturating a
x16 link. Using PLX’s Software Development Kit
(www.plxtech.com/sdk), designers can create custom
traffic scripts for system bring-up and debug. Fully
integrated into the PEX8733, the Packet Generator proves
to be a very convenient on-chip debug tool. Furthermore,
the Packet Generator can be used to create PCIe traffic to
test and debug other devices in the system.


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