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MAX1816 Datasheet(PDF) 32 Page - Maxim Integrated Products |
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MAX1816 Datasheet(HTML) 32 Page - Maxim Integrated Products |
32 / 49 page Dual Step-Down Controllers Plus Linear- Regulator Controller for Notebook Computers 32 ______________________________________________________________________________________ Shutdown Control (SKP1/ S SD DN N, SKP2/ S SD DN N, and LIN/S SD DN N) If BUCK2 is used, always start BUCK2 before starting BUCK1. When SKP1/SDN goes below 0.5V, BUCK1 enters low-power shutdown mode. PGOOD goes low immediately. The output voltage ramps down to zero in 25mV steps at the clock rate set by RTIME. Thirty-two clocks after the DAC reaches the zero setting, DL1 is forced to VDD, and DH1 is forced low. When SKP1/SDN goes above 1.4V or floats, the DAC target is evaluated and switching begins. The slew-rate controller ramps up from zero in 25mV steps to the selected DAC code value. There is no traditional soft-start (variable current- limit) circuitry, so full output current is available immedi- ately. Floating SKP1/SDN causes BUCK1 to operate in low-noise forced-PWM mode. Forcing SKP1/SDN above 2.8V enables skip mode operation. When SKP2/SDN goes below 0.5V, BUCK2 enters shut- down mode. In shutdown mode, DL2 is forced to VDD if overvoltage protection is enabled. If OVPSET is con- nected to VCC, overvoltage protection is disabled and DL2 is forced low in shutdown mode. When LIN/SDN goes below 0.8V, the linear regulator of the MAX1816/MAX1994 enters shutdown mode. In shutdown mode, LINBSE is forced to a high-impedance state preventing sufficient drive to the external PNP pass transistor in the regulator. LINGOOD is forced low within 10µs (typ) when LIN/SDN goes low. Forcing LIN/SDN above 2.4V turns on the linear regulator. Power-On Reset Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the MAX1816/MAX1994 for operation. VCC undervoltage lockout (UVLO) circuitry inhibits switching, forces PGOOD low, and forces the DL1 gate driver high (to enforce output overvoltage protection). The DL2 gate driver is also forced high if OVP is enabled. When VCC rises above 4.25V, the DAC inputs are sampled and the output voltage begins to slew to the DAC setting. For automatic startup, the battery voltage should be present before VCC. If the MAX1816/MAX1994 attempt to bring the output into regulation without the battery voltage present, the fault latch will trip. Toggling any of the shut- down control pins resets the fault latch. Power Valid Outputs (PGOOD and LINGOOD) PGOOD is an open-drain power-good output. Table 4 describes the behavior of PGOOD with respect to the logic inputs. Window comparators on FBS and OUT2 (FB2) control the PGOOD output. If BUCK1 and BUCK2 are in regulation then PGOOD is high, except during power-up and power-down. The PGOOD output goes low if FBS or OUT2 (FB2) is outside a window of ±10% about the nominal set point (see the DAC Inputs and Internal Multiplexers and Adjusting BUCK2 Output Voltage sections). PGOOD is forced low when SKP1/SDN is low. If SKP2/SDN is low, then OUT2 (FB2) does not affect PGOOD. Normally, PGOOD is forced high during all VID transitions, and stays high for 4 clock periods after the DAC count is equalized. If BUCK2 goes out of regu- lation during these conditions, then PGOOD goes low as a consequence. A pullup resistor on PGOOD caus- es additional finite shutdown current. The following conditions must all be met for PGOOD to go high: • VCC must be above UVLO. • SKP1/SDN must be greater than 1.4V or unconnected. • The output of BUCK1 must be within a window of ±10% about the nominal set point. • PGOOD is forced high during DAC code transitions of BUCK1. The “blanking” period persists for N+4 RTIME clock cycles. Blanking does not occur during power-up and power-down. • If SKP2/SDN is not low, then OUT2 (FB2) must be within a window of ±10% about the nominal set point. • When enabled, a fault on OUT2 overrides the blank- ing on BUCK1. LINGOOD is an open-drain power-good output for the linear regulator. LINGOOD goes high at least 1ms after the internal comparator signals that the output is in reg- ulation. In normal operation, if the internal comparator signals that the circuit is out of regulation, LINGOOD goes low within approximately 10µs (typ). If LIN/SDN goes low, LINGOOD is immediately forced low. Note that all three regulators are forced off when a fault is detected. DL_ are forced high, DH_ are forced low, and the linear regulator is turned off. (See the Output Overvoltage Protection, Output Undervoltage Protection, UVLO, and Thermal Fault Protection sections). DAC Inputs and Internal Multiplexers (SUS) The MAX1816/MAX1994 have a unique internal VID input multiplexer (mux) that can select one of two different VID DAC code settings for different processor states. When the logic level at SUS is low, the mux selects the VID DAC code settings from the D0–D4 inputs (Table 5). Do not leave D0–D4 floating—use 100k Ω pullup resistors if the inputs float. When SUS is high, the suspend mode mux selects the VID DAC code settings from the S0/S1 input decoder. The outputs of the decoder are determined by |
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