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ATF-331M4 Datasheet(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED

Part No. ATF-331M4
Description  Low Noise Pseudomorphic HEMT in a Miniature Leadless Package
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Maker  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Homepage  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

ATF-331M4 Datasheet(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED

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ATF-331M4 Absolute Maximum Ratings[1]
Symbol
Parameter
Units
Absolute
Maximum
VDS
Drain-Source Voltage [2]
V
5.5
VGS
Gate-Source Voltage [2]
V
-5
VGD
Gate Drain Voltage [2]
V
-5
IDS
Drain Current [2]
mA
Idiss[3]
Pdiss
Total Power Dissipation [4]
mW
400
Pin max.
RF Input Power
dBm
20
TCH
Channel Temperature [5]
°C
160
TSTG
Storage Temperature
°C
-65 to 160
jc
Thermal Resistance [6]
°C/W
200
Notes:
1. Operation of this device above any one of
these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. VGS = 0 V
4. Source lead temperature is 25°C. Derate
5 mW/°C for TL > 40°C.
5. Please refer to failure rates in reliability
data sheet to assess the reliability impact
of running devices above a channel
temperature of 140°C.
6. Thermal resistance measured using 150°C
Liquid Crystal Measurement method.
Product Consistency Distribution Charts[8, 9]
VDS (V)
Figure 1. Typical Pulsed I-V Curves[7].
(VGS = -0.2 V per step)
02
4
6
8
500
400
300
200
100
0
-0.6 V
0 V
+0.6 V
NF (dBm)
Figure 2. NF @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 0.6, USL = 0.8.
0.2
0.4
0.5
0.6
0.7
0.3
0.8
0.9
100
80
60
40
20
0
-3 Std
+3 Std
Cpk = 1.05
Stdev = 0.07
OIP3 (dBm)
Figure 3. OIP3 @ 2 GHz, 4 V, 60 mA.
LSL = 28.5, Nominal = 31.0, USL = 36.0
28
32
30
34
36
-3 Std
+3 Std
150
120
90
60
30
0
Cpk = 1.00
Stdev = 1.07
GAIN (dB)
Figure 4. Gain @ 2 GHz, 4 V, 60 mA.
LSL = 13.5, Nominal = 15.0, USL = 16.5
13
15
14
16
17
-3 Std
+3 Std
120
100
80
60
40
20
0
Cpk = 4.37
Stdev = 1.11
Notes:
8. Distribution data sample size is 349 samples from 4 different wafers. Future wafers allocated to this product may have nominal values anywhere
within the upper and lower spec limits.
9. Measurements made on production test board. This circuit represents a trade-off between an optimal noise match and a realizeable match based
on production test requirements. Circuit losses have been de-embedded from actual measurements.
Note:
7. Under large signal conditions, VGS may
swing positive and the drain current may
exceed Idss.These conditions are acceptable
as long as the Maximum Pdiss and Pin max
ratings are not exceeded.


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