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MAX1458 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX1458 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 20 page FSOTC Compensation Silicon piezoresistive transducers (PRTs) exhibit a large positive input resistance tempco (TCR) so that, while under constant current excitation, the bridge voltage (VBDRIVE) increases with temperature. This depen- dence of VBDRIVE on the sensor temperature can be used to compensate the sensor temperature errors. PRTs also have a large negative full-span output sensi- tivity tempco (TCS) so that, with constant voltage exci- tation, full-span output (FSO) will decrease with temperature, causing a full-span output temperature coefficient (FSOTC) error. However, if the bridge volt- age can be made to increase with temperature at the same rate that TCS decreases with temperature, the FSO will remain constant. FSOTC compensation is accomplished by resistor RFTC and the FSOTC DAC, which modulate the excita- tion reference current at ISRC as a function of tempera- ture (Figure 3). FSO DAC sets VISRC and remains constant with temperature while the voltage at FSOTC varies with temperature. FSOTC is the buffered output of the FSOTC DAC. The reference DAC voltage is VBDRIVE, which is temperature dependent. The FSOTC DAC alters the tempco of the current source. When the tempco of the bridge voltage is equal in magnitude and opposite in polarity to the TCS, the FSOTC errors are compensated and FSO will be constant with tempera- ture. OFFSET TC Compensation Compensating offset TC errors involves first measuring the uncompensated offset TC error, then determining the percentage of the temperature-dependent voltage VBDRIVE that must be added to the output summing junction to correct the error. Use the Offset TC DAC to adjust the amount of BDRIVE voltage that is added to the output summing junction (Figure 2). Analog Signal Path The fully differential analog signal path consists of four stages: • Front-end summing junction for coarse offset correction • 3-bit PGA with eight selectable gains ranging from 41 through 230 • Three-input-channel summing junction • Differential to single-ended output buffer (Figure 2) Coarse Offset Correction The sensor output is first fed into a differential summing junction (INM (negative input) and INP (positive input)) with a CMRR > 90dB, an input impedance of approxi- mately 1M Ω, and a common-mode input voltage range from VSS to VDD. At this summing junction, a coarse off- set-correction voltage is added, and the resultant volt- age is fed into the PGA. The 3-bit (plus sign) input-referred Offset DAC (IRO DAC) generates the coarse offset-correction voltage. The DAC voltage ref- erence is 1.25% of VDD; thus, a VDD of 5V results in a front-end offset-correction voltage ranging from -63mV to +63mV, in 9mV steps (Table 1). To add an offset to the input signal, set the IRO sign bit high; to subtract an offset from the input signal, set the IRO sign bit low. The IRO DAC bits (C2, C1, C0, and IRO sign bit) are programmed in the configuration register (see Internal EEPROM section). 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner _______________________________________________________________________________________ 5 PRESSURE PMIN PMAX FULL-SCALE (FS) 4.5 0.5 FULL-SPAN OUTPUT (FSO) OFFSET Figure 1. Typical Pressure-Sensor Output SOTC BDRIVE 1.25% VDD SOFF ± ± A2 INP INM A1 A0 PGA Σ Σ A = 1 OUT LIMIT A = 2.3 A = 2.3 OFFTC DAC IRO DAC VDD Offset DAC Figure 2. Signal-Path Block Diagram |
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