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MAX144 Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX144 Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 16 page _______________Detailed Description The MAX144/MAX145 analog-to-digital converters (ADCs) use a successive-approximation conversion (SAR) technique and on-chip track-and-hold (T/H) structure to convert an analog signal to a serial 12-bit digital output data stream. This flexible serial interface provides easy interface to microprocessors (µPs). Figure 2 shows a simplified functional diagram of the internal architecture for both the MAX144 (2 channels, single-ended) and the MAX145 (1 channel, pseudo-differential). Analog Inputs: Single-Ended (MAX144) and Pseudo-Differential (MAX145) The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuit of Figure 3. In single-ended mode (MAX144), both chan- nels CH0 and CH1 are referred to GND and can be connected to two different signal sources. Following the power-on reset, the ADC is set to convert CH0. After CH0 has been converted, CH1 will be converted and the conversions will continue to alternate between channels. Channel switching is performed by toggling the CS/SHDN pin. Conversions can be performed on the same channel by toggling CS/SHDN twice between conversions. If only one channel is required, CH0 and CH1 may be connected together; however, the output data will still contain the channel identification bit (before the MSB). For the MAX145, the input channels form a single differ- ential channel pair (CH+, CH-). This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side IN- must remain stable within ±0.5LSB (±0.1LSB for optimum results) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans from when CS/SHDN falls to the falling edge of the second clock cycle (external clock mode) or from when CS/SHDN falls to the first falling edge of SCLK (internal clock mode). At the end of the acquisition interval, the T/H switch opens, retain- ing charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAX _______________________________________________________________________________________ 7 6k CL DOUT a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z 6k CL DOUT GND GND VDD b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z Figure 1. Load Circuits for Enable and Disable Time MAX144 MAX145 12-BIT SAR ADC SCLK ( ) ARE FOR MAX145 IN OUT ANALOG INPUT MUX (2 CHANNEL) CH0 (CH+) CH1 (CH-) REF T/H CONTROL LOGIC SCLK CS/SHDN INTERNAL CLOCK OUTPUT REGISTER DOUT Figure 2. Simplified Functional Diagram CH0 (CH+) CH1 (CH-) ( ) ARE FOR MAX145 SINGLE-ENDED MODE: CH0, CH1 = IN+; GND = IN- DIFFERENTIAL-ENDED MODE: CH+ = IN+; CH- = IN- RIN 9k Ω ZERO REF GND TRACK HOLD COMPARATOR TO SAR T/H CHOLD 16pF INPUT MUX 12-BIT CAPACITIVE DAC CSWITCH CONTROL LOGIC MAX144 MAX145 Figure 3. Analog Input Channel Structure |
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