At VREF, the DC input resistance is a minimum of 18k

Ω.

During conversion, an external reference at VREF must

deliver up to 350µA DC load current and have 10

Ω or

less output impedance. If the reference has a higher

output impedance or is noisy, bypass it close to the

VREF pin with a 4.7µF capacitor.

Using the REFADJ input makes buffering the external

reference unnecessary. To use the direct VREF input,

power-down, the input bias current to REFADJ can be

REFADJ to AGND to minimize the input bias current in

power-down.

Transfer Function

Table 7 shows the full-scale voltage ranges for unipolar

and bipolar modes.

The external reference must have a temperature coeffi-

cient of 4ppm/°C or less to achieve accuracy to within

1LSB over the 0°C to +70°C commercial temperature

range.

Figure 16 depicts the nominal, unipolar input/output

(I/O) transfer function, and Figure 17 shows the bipolar

input/output transfer function. Code transitions occur

halfway between successive-integer LSB values.

Output coding is binary, with 1LSB = 610µV (2.500V /

4096) for unipolar operation, and 1LSB = 610 µV

[(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation.

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards.

Wire-wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

Figure 18 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at AGND, separate from the logic

ground. Connect all other analog grounds and DGND

to the star ground. No other digital system ground

should be connected to this ground. For lowest-noise

operation, the ground return to the star ground’s power

supply should be low impedance and as short as

possible.

affect the high-speed comparator in the ADC. Bypass

the supply to the star ground with 0.1µF and 1µF

capacitors close to pin 1 of the MAX1246/MAX1247.

Minimize capacitor lead lengths for best supply-noise

rejection. If the power supply is very noisy, a 10

Ω resis-

tor can be connected as a lowpass filter (Figure 18).

High-Speed Digital Interfacing with QSPI

The MAX1246/MAX1247 can interface with QSPI using

CPHA = 0). This QSPI circuit can be programmed to do a

conversion on each of the four channels. The result is

stored in memory without taxing the CPU, since QSPI

incorporates its own microsequencer.

The MAX1246/MAX1247 are QSPI compatible up to its

maximum external clock frequency of 2MHz.

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

______________________________________________________________________________________

19

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

1

2

3

0

(COM)

FS

FS - 3/2LSB

FS = VREF + COM

ZS = COM

INPUT VOLTAGE (LSB)

1LSB =

VREF

4096

Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF

+ COM, Zero Scale (ZS) = COM

UNIPOLAR MODE

BIPOLAR MODE

Full Scale

Zero Scale

Positive

Zero

Negative

Full Scale

Scale

Full Scale

VREF + COM

COM

VREF / 2

COM

-VREF / 2

+ COM

+ COM

Table 7. Full Scale and Zero Scale