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M14D5121632A-2K Datasheet(PDF) 12 Page - Elite Semiconductor Memory Technology Inc. |
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M14D5121632A-2K Datasheet(HTML) 12 Page - Elite Semiconductor Memory Technology Inc. |
12 / 64 page ESMT M14D5121632A (2K) Elite Semiconductor Memory Technology Inc. Publication Date : May 2014 Revision : 1.4 12/64 AC Timing Parameter & Specifications - Contiuned -1.3 -1.5 Parameter Symbol Min. Max. Min. Max. Unit Note Active to Precharge command tRAS 60 70K 45 70K ns Active to Active command (same bank) tRC 80 58.125 ns Auto Refresh row cycle time tRFC 150 130 ns Active to Read, Write delay tRCD 13.3 13.5 ns Precharge command period tRP 13.3 13.5 ns Active bank A to Active bank B command tRRD 12 10 ns Write recovery time tWR 15 15 ns Write data in to Read command delay tWTR 7.5 7.5 ns 19 Col. address to Col. address delay tCCD 4 2 tCK Average periodic Refresh interval ( 0℃ ≦TC ≦ +85℃ ) tREFI 7.8 7.8 us Average periodic Refresh interval (+85℃ <TC ≦ +95℃) tREFI 3.9 3.9 us Write preamble tWPRE 0.35 0.35 tCK (avg) Write postamble tWPST 0.4 0.6 0.4 0.6 tCK (avg) DQS Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK (avg) 11 DQS Read postamble tRPST 0.4 0.6 0.4 0.6 tCK (avg) 12 Load Mode Register / Extended Mode Register cycle time tMRD 2 5 tCK Auto Precharge write recovery + Precharge time tDAL X - X tCK 1, 20 Internal Read to Precharge command delay tRTP 10 7.5 ns Exit Self Refresh to Read command tXSRD 200 200 tCK Exit Self Refresh to non-Read command tXSNR tRFC + 10 tRFC + 10 ns Exit Precharge Power-Down to any non-Read command tXP 5 5 tCK Exit Active Power-Down to Read command tXARD 5 5 tCK 3 Exit active power-down to Read command (slow exit / low power mode) tXARDS 12 - AL 10 - AL tCK 2,3 CKE minimum pulse width (high and low pulse width) tCKE 5 5 tCK |
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