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M13S128324A-2M Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 7 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
7/48
IDD Specifications
Version
Symbol
-3.6
-4
-5
-6
Unit
IDD0
235
210
175
145
mA
IDD1
245
220
190
180
mA
IDD2P
40
40
40
40
mA
IDD2F
135
120
115
95
mA
IDD2Q
135
120
115
95
mA
IDD3P
60
55
50
45
mA
IDD3N
150
130
120
110
mA
IDD4R
440
400
350
300
mA
IDD4W
470
430
380
330
mA
IDD5
320
290
270
250
mA
IDD6
5
5
5
5
mA
IDD7
500
460
410
360
mA
Input / Output Capacitance
(VDD = 2.375V~2.625V, VDDQ =2.375V~2. 625V, TA = 25 C
° , f = 1MHz)
(VDD = 2.5V~2.7V, VDDQ =2.5V~2.7V, TA = 25 C
° , f = 1MHz (for speed -3.6))
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0~A11, BA0~BA1, CKE,
CS , RAS , CAS , WE )
CIN1
1
4
pF
Input capacitance (CLK, CLK )
CIN2
1
5
pF
Data & DQS input/output capacitance
COUT
1
6.5
pF
Input capacitance (DM)
CIN3
1
6.5
pF


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