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M13S128324A-2M Datasheet(PDF) 47 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 47 Page - Elite Semiconductor Memory Technology Inc.

 
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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
47/48
Revision History
Revision
Date
Description
0.1
2009.12.10
Original
0.2
2009.12.23
Delete CAS Latency 4
1.0
2010.03.05
Delete “Preliminary”
1.1
2010.03.29
Add package description into ball configuration
1.2
2010.05.27
1. Modify the specification of tDQSQ for -5
2. Distribute tRCD into tRCDRD and tRCDWR
1.3
2011.08.09
1. Add operating ambient temperature into absolute maximum
ratings
2. Correct Active/Precharge Power Down Mode of command
truth table


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