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M13S128324A-2M Datasheet(PDF) 43 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 43 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
43/48
Power up & Initialization Sequence (based on DDR400)
VDDQ
VREF
A0 - A 7
A9 - A n
Po w e r-u p :
VDD a n d
CL K s t a b l e
BA 0 , BA 1
E x t e nde d
M ode
Re g i s t e r
Se t
COMMAND
DM
DQ S
t MRD
t MRD
20 0 c y c le s o f C L K * *
L oad
Mod e
R e gi ster
Re s e t D L L
(w i t h A 8 = H )
L oad
Mo d e
R egis t er
( w ith A 8= L)
VDD
A8
T=20 0us
VTT
(system*)
tVDT >=0
CLK
CLK
CKE
NOP
t CH
t CL
t CK
t IS t IH
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
t IH
t IS
CODE
t IH
t IS
LV C O M S L O W L EV EL
CODE
CODE
RA
t IH
t IS
CODE
CODE
CODE
RA
BA0=L,
BA1=L
BA
t IH
t IS
t IH t IS
BA0=L,
BA1=L
H i gh- Z
DQ
Hi g h - Z
t RP
t RF C
t MR D
ALL BANKS
ALL BANKS
t RF C
BA0=H,
BA1=L
t IH
t IS
:D o n ’ t c a r e
10 122 B 3 2R . B
Notes:
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CLK are required before an executable command
can be applied. The two Auto Refresh commands may be moved to follow the first MRS but precede the second
PRECHARGE ALL command.


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