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M13S128324A-2M Datasheet(PDF) 4 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 4 Page - Elite Semiconductor Memory Technology Inc.

 
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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
4/48
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
Voltage on inputs relative to VSS
VINPUT
-1.0 ~ 3.6
V
Voltage on I/O pins relative to VSS
VIO
-0.5 ~ VDDQ+0.5
V
Operating ambient temperature
TA
0 ~ +70
C
°
Storage temperature
TSTG
-55 ~ +150
C
°
Power dissipation
PD
2
W
Short circuit current
IOS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 C
°)
Min
Max
Parameter
Symbol
-3.6
-4/5/6
-3.6
-4/5/6
Unit
Note
Supply voltage
VDD
2.5
2.375
2.7
2.625
V
I/O Supply voltage
VDDQ
2.5
2.375
2.7
2.625
V
I/O Reference voltage
VREF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage (system)
VTT
VREF - 0.04
VREF + 0.04
V
2
Input logic high voltage
VIH (DC)
VREF + 0.15
VDDQ + 0.3
V
Input logic low voltage
VIL (DC)
-0.3
VREF - 0.15
V
Input Voltage Level, CLK and CLK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CLK and CLK inputs
VID (DC)
0.36
VDDQ + 0.6
V
3
V–I Matching: Pullup to Pulldown Current Ratio
VI (Ratio)
0.71
1.4
-
4
Input leakage current: Any input 0V ≤ VIN ≤ VDD
(All other pins not tested under = 0V)
IL
-2
2
μ A
Output leakage current
(DQs are disable; 0V ≤ VOUT ≤ VDDQ)
IOZ
-5
5
μ A


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