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M13S128324A-2M Datasheet(PDF) 35 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 35 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
35/48
Write with Auto Precharge (@ BL=8)
CK E
CS
RA S
CA S
BA 0 , BA 1
WE
DQ S
DQ
01
234
567
8910
HI GH
DM
CO M M A N D
A 8 /A P
AD D R
(A 0 ~ A n )
BAa
Da 4
Da 5
Da 7
Da 6
t RP
Da 0
Da 1
Da 3
Da 2
ACTIVE
WRITE
Ca
A u to pr ec har g e s t ar t
No t e 1
BAa
Ra
t WR
CL K
CL K
t DA L
:D o n ’ t c a r e
10 12 2 B 3 2 R . B
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.


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