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M13S128324A-2M Datasheet(PDF) 25 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 25 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
25/48
Read with Auto Precharge
If a read with auto precharge command is initiated, the DDR SDRAM automatically enters the precharge operation BL/2 clock later
from a read with auto precharge command when tRAS (min) is satisfied. If not, the start point of precharge operation will be delayed
until tRAS (min) is satisfied. Once the precharge operation has started the bank cannot be reactivated and the new command can not
be asserted until the precharge time (tRP) has been satisfied.
<Burst Length = 4, CAS Latency = 2 & 2.5>
01
23
4
5
67
8
9
COM M AND
Bank A
ACTIVE
NOP
NOP
NO P
NOP
NO P
NOP
NOP
Read A
Auto Precharge
CLK
CL K
DQS
DQ's
CAS Latency = 2
CAS Latency = 2.5
DOUT 0
t RP
NOP
* Bank can be reactivated at
completion of precharge
Auto-Precharge starts
Hi -Z
Hi -Z
t RA S ( mi n )
DOUT 1 DOUT 2 DOUT 3
DQS
DQ's
DOUT 0
Hi -Z
Hi - Z
DOUT 1 DOUT 2 DOUT 3
When the Read with Auto Precharge command is issued, new command can be asserted at 4, 5 and 6 respectively as follow.
For the same bank
For the different bank
Asserted
Command
4
5
6
4
5
6
READ
READ
Illegal
Illegal
Legal
Legal
Legal
READ with AP
*1
READ with AP
Illegal
Illegal
Legal
Legal
Legal
Active
Illegal
Illegal
Illegal
Legal
Legal
Legal
Precharge
Legal
Legal
Illegal
Legal
Legal
Legal
Note 1: AP = Auto Precharge


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