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M13S128324A-2M Datasheet(PDF) 21 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 21 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
21/48
Write Interrupted by a Write
A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address and data will be written into the device until the programmed burst length is satisfied.
<Burst Length = 4>
01
23
4
5
6
7
8
CO M M A ND
DQ S
DQ ' s
NOP
NOP
NO P
NO P
NOP
NO P
N O P
DIN A0
WRIT E A
D IN A1
D IN B 2
DIN B3
D IN B0
DIN B1
CL K
CL K
1t CK
Hi - Z
Hi- Z
WR IT E B


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