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M13S128324A-2M Datasheet(PDF) 18 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 18 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
18/48
Read
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating
CS , RAS , CAS , and deasserting WE at the same clock rising edge as described in the command truth table. The length of the
burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating
CS , RAS , CAS , and WE at the same clock rising edge as describe in the command truth table. The length of the burst will be
determined by the values programmed during the MRS command.
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is issued by
asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after tRCDRD from the bank
activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or
interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ command, and the
consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM until the burst length
is completed.
<Burst Length = 4, CAS Latency = 3>
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the clock
(CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write
cycle. The first data of a burst write cycle must be applied on the DQ pins tDS prior to data strobe edge enabled after tDQSS from the
rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be supplied on each subsequent
falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data
supplied to the DQ pins will be ignored.
<Burst Length = 4>
Note * 1: The specific requirement is that DQS be valid (High or Low) on or before this CLK edge. The case shown (DQS going from
High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS
could be High at this time, depending on tDQSS.
0
1
23
4
5
67
8
COM M A N D
R EAD A
NOP
NO P
NO P
NO P
NOP
NO P
NO P
NO P
CL K
CL K
CA S L a t e n c y = 3
DQS
DQ ' s
D OU T 0 D OU T 1 D OU T 2 D OU T 3
tRP RE
t RP S T
01
23
4
5
6
7
8
C O MMA N D
NOP
WR IT E A
NO P
NOP
NO P
NO P
NO P
NO P
CL K
CL K
DQS
DQ' s
D IN 0
WR IT E B
D IN1
DIN2
D IN3
tDQ S S m ax
tWP RE S *1
*1
*1
D IN 0
D IN1
DIN 2
D IN3


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