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M13S128324A-2M Datasheet(PDF) 17 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 17 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
17/48
Precharge
The precharge command is used to precharge or close a bank that has activated. The precharge command is issued when CS ,
RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each
bank respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used to define which bank is precharged
when the command is initiated. For write cycle, tWR(min) must be satisfied until the precharge command can be issued. After tRP from
the precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by bank address bits
A8/AP
BA1
BA0
Precharge
0
0
0
Bank A Only
0
0
1
Bank B Only
0
1
0
Bank C Only
0
1
1
Bank D Only
1
X
X
All Banks
No Operation & Device Deselect
The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs.
The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS , CAS and WE . For both Deselect and
NOP the device should finish the current operation when this command is issued.
Bank / Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock
(CLK). The DDR SDRAM has two independent banks, so Bank Select addresses (BA0, BA1) are required. The Bank Activation
command must be applied before any Read or Write operation is executed. The Bank Activation command to the first Read or Write
command must meet or exceed the minimum of RAS to CAS delay time (tRCDRD or tRCDWR min). Once a bank has been activated,
it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
Add r es s
01
2
3
Co m m a n d
Ba n k A
Ro w A ddr .
Ba n k A
Row. A d d r .
Ba nk B
Ro w A d d r .
Ba nk A
A c ti v a te
NO P
Ba n k B
Act i v a t e
NO P
Ba n k A
Ac t i v a t e
RA S - C A S d e l a y (
t RC DW R )
RA S - RA S d e l a y (
t RRD )
RO W C y c l e T i m e (
t RC )
:D o n ' t C a r e
CL K
CL K
NO P
Tn
Tn+1
Tn+2
Ban k A
Col . Ad dr .
Wr i t e A
wi th A P


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