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M13S128324A-2M Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13S128324A-2M
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13S128324A-2M Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc.

 
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ESMT
M13S128324A (2M)
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
1/48
DDR SDRAM
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V
VDD = 2.5V ~ 2.7V, VDDQ = 2.5V ~ 2.7V (for speed -3.6)
Auto & Self refresh
32ms refresh period (4K cycle)
2.5V I/O (SSTL_2 compatible)
Ordering Information
Product ID
Max Freq.
VDD
Package
Comments
M13S128324A -3.6BG2M
275MHz (DDR550)
2.6V
M13S128324A -4BG2M
250MHz (DDR500)
2.5V
M13S128324A -5BG2M
200MHz (DDR400)
2.5V
M13S128324A -6BG2M
166MHz (DDR333)
2.5V
144 ball FBGA
Pb-free


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