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M13L2561616A-2A Datasheet(PDF) 8 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 8 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
8/49
AC Operation Conditions & Timing Specifications
AC Operation Conditions
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.45
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
VREF - 0.45
V
Input Differential Voltage, CLK and CLK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CLK and CLK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes:
1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of
the same.
AC Overshoot / Undershoot Specification
Value
Parameter
Pin
-4/ -5 / -6
Unit
Address, Control
1.5
V
Maximum peak amplitude allowed for overshoot
Data, Strobe, Mask
1.2
V
Address, Control
1.5
V
Maximum peak amplitude allowed for undershoot
Data, Strobe, Mask
1.2
V
Address, Control
4.5
V-ns
Maximum overshoot area above VDD
Data, Strobe, Mask
2.4
V-ns
Address, Control
4.5
V-ns
Maximum undershoot area below VSS
Data, Strobe, Mask
2.4
V-ns


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