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M13L2561616A-2A Datasheet(PDF) 7 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 7 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
7/49
IDD Specifications
Version
Symbol
-4
-5
-6
Unit
IDD0
90
80
70
mA
IDD1
120
110
100
mA
IDD2P
6
6
6
mA
IDD2F
50
50
50
mA
IDD2Q
50
50
50
mA
IDD3P
30
25
20
mA
IDD3N
60
55
50
mA
IDD4R
140
130
120
mA
IDD4W
140
130
120
mA
IDD5
150
140
130
mA
IDD6
3
3
3
mA
IDD7
230
220
210
mA
Input / Output Capacitance
Parameter
Package
Symbol
Min
Max
Delta Cap
(max)
Unit
Note
TSOP
2.5
4.5
pF
Input capacitance (A0~A12, BA0~BA1,
CKE, CS , RAS , CAS , WE )
BGA
CIN1
2
4
0.5
pF
1,4
TSOP
2.5
4.5
pF
Input capacitance (CLK, CLK )
BGA
CIN2
2
4
0.25
pF
1,4
TSOP
1.5
3.5
pF
Data & DQS input/output capacitance
BGA
COUT
1
3
0.5
pF
1,2,3,4
TSOP
1.5
3.5
pF
Input capacitance (DM)
BGA
CIN3
1
3
0.5
pF
1,2,3,4
Notes:
1. These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and
DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameter is sampled. VDDQ = 3.3V ± 0.3V, VDD = 3.3V ± 0.3V. f=100MHz, TA =25°C, VOUT(DC) = VDDQ/2, VOUT
(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to
facilitate trace matching at the board level).


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