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M13L2561616A-2A Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
6/49
IDD Parameters and Test Conditions
Test Condition
Symbol
Note
Operating Current (one bank Active - Precharge):
tRC = tRC (min); tCK = tCK (min); DQ, DM, and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles; CS = high between valid commands.
IDD0
Operating Current (one bank Active - Read - Precharge):
One bank open; BL = 4; tRC = tRC (min); tCK = tCK (min); IOUT = 0mA;
Address and control inputs changing once per deselect cycle; CS = high between valid commands
IDD1
2
Precharge Power-down Standby Current:
All banks idle; Power-down mode; tCK = tCK (min); CKE VIL(max); VIN = VREF for DQ, DQS and DM.
IDD2P
Precharge Floating Standby Current:
CS
VIH(min); All banks idle; CKE VIH(min); tCK = tCK (min);
Address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS, and DM.
IDD2F
Precharge Quiet Standby Current:
CS
VIH(min); All banks idle; CKE VIH(min); tCK = tCK (min);
Address and other control inputs stable at
VIH(min) or VIL(max); VIN = VREF for DQ, DQS, and DM.
IDD2Q
Active Power-down Standby Current:
One bank active; Power-down mode; CKE
VIL(max); tCK = tCK (min); VIN = VREF for DQ, DQS, and DM.
IDD3P
Active Standby Current:
CS
VIH(min); CKE VIH(min); One bank active; tRC = tRAS (max); tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle.
IDD3N
Operating Current (burst read):
BL = 2; Continuous burst reads; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min); IOUT = 0mA;
50% of data changing on every transfer.
IDD4R
Operating Current (burst write):
BL = 2; Continuous burst writes; One bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (min);
DQ, DM, and DQS inputs changing twice per clock cycle; 50% of input data changing at every transfer.
IDD4W
Auto Refresh Current:
tRC = tRFC(min)
IDD5
Self Refresh Current:
CKE
0.2V; external clock on; tCK = tCK (min)
IDD6
1
Operating Current (Four bank operation):
Four-bank interleaving READs (burst = 4) with auto precharge; tRC = tRC (min); tCK = tCK (min);
Address and control inputs change only during ACTIVE, READ, or WRITE commands; IOUT = 0mA.
IDD7
2
Notes:
1. Enable on-chip refresh and address counters.
2. Random address is changing; 50% of data is changing at every transfer.


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