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M13L2561616A-2A Datasheet(PDF) 39 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13L2561616A-2A Datasheet(HTML) 39 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
39/49
Read Interrupted by Precharge (@ BL=8)
CK E
CS
RA S
CA S
BA 0 , B A 1
WE
DQ S ( C L = 2 )
DQ ( C L = 2 )
01
23
4
5
6
7
8
9
10
HI G H
C O MMA N D
A 10 /AP
AD D R
(A 0~ A n )
BAa
Qa 0
Qa 1
READ
BAb
Ca
PRE
CHARGE
CL K
CL K
Qa 2
Q a 3
Qa 4
Q a 5
DM
2tCK Valid
DQ S(C L =2 . 5 )
D Q ( C L= 2 . 5)
Qa 0
Qa 1
Qa 2
Q a 3
Qa 4
Q a 5
2.5 tCK Valid
:D o n ’ t c a r e
10 1 2 2 B 16 R.B
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst
and when a new Bank Activate command may be issued to the same bank.
1.
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS Precharge time).
2.
When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the
last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same
bank after tRP.


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