Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

M13L2561616A-2A Datasheet(PDF) 39 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
Download  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13L2561616A-2A Datasheet(HTML) 39 Page - Elite Semiconductor Memory Technology Inc.

Back Button M13L2561616A-2A Datasheet HTML 35Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 36Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 37Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 38Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 39Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 40Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 41Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 42Page - Elite Semiconductor Memory Technology Inc. M13L2561616A-2A Datasheet HTML 43Page - Elite Semiconductor Memory Technology Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 49 page
background image
ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
39/49
Read Interrupted by Precharge (@ BL=8)
CK E
CS
RA S
CA S
BA 0 , B A 1
WE
DQ S ( C L = 2 )
DQ ( C L = 2 )
01
23
4
5
6
7
8
9
10
HI G H
C O MMA N D
A 10 /AP
AD D R
(A 0~ A n )
BAa
Qa 0
Qa 1
READ
BAb
Ca
PRE
CHARGE
CL K
CL K
Qa 2
Q a 3
Qa 4
Q a 5
DM
2tCK Valid
DQ S(C L =2 . 5 )
D Q ( C L= 2 . 5)
Qa 0
Qa 1
Qa 2
Q a 3
Qa 4
Q a 5
2.5 tCK Valid
:D o n ’ t c a r e
10 1 2 2 B 16 R.B
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst
and when a new Bank Activate command may be issued to the same bank.
1.
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on
the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after tRP (RAS Precharge time).
2.
When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock
edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the
last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same
bank after tRP.


Similar Part No. - M13L2561616A-2A

ManufacturerPart No.DatasheetDescription
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
More results

Similar Description - M13L2561616A-2A

ManufacturerPart No.DatasheetDescription
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13S128324A-2M ESMT-M13S128324A-2M Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
M13S2561616A-2S ESMT-M13S2561616A-2S Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
M13S5121632A-2S ESMT-M13S5121632A-2S Datasheet
705Kb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W9412G2IB4 WINBOND-W9412G2IB4 Datasheet
832Kb / 50P
   Double Data Rate architecture; two data transfers per clock cycle
W9412G6JH-5 WINBOND-W9412G6JH-5 Datasheet
1Mb / 53P
   Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13S2561616A-2A ESMT-M13S2561616A-2A Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W9751G6KB-25 WINBOND-W9751G6KB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W631GG6KB-15 WINBOND-W631GG6KB-15 Datasheet
3Mb / 158P
   Double Data Rate architecture: two data transfers per clock cycle
W972GG6JB-25 WINBOND-W972GG6JB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
More results


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz