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M13L2561616A-2A Datasheet(PDF) 34 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
Download  49 Pages
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 34 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
34/49
Read with Auto Precharge (@ BL=8)
CK E
CS
RA S
CA S
BA 0 , BA 1
WE
DQ S ( C L = 2 )
DQ ( C L = 2 )
01
234
567
8910
HI GH
DM
CO M M A ND
A 10 /A P
AD D R
(A 0~ A n )
BAa
Qa 4
Q a 5
Qa 7
Qa 6
BAa
t RP
Qa 0
Qa 1
Q a 3
Qa 2
ACTIVE
READ
Ca
Auto pr ec har g e s t ar t
No t e 1
CL K
CL K
Ra
DQ S( C L = 2 . 5 )
D Q ( C L = 2. 5)
Qa 4
Q a 5
Qa 7
Qa 6
Qa 0
Qa 1
Qa 3
Qa 2
:D o n ’ t c a r e
10 1 2 2B 1 6 R . B
Note: 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of another activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.


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