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M13L2561616A-2A Datasheet(PDF) 24 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 24 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
24/49
Burst Terminate
The burst terminate command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the
clock (CLK). The burst terminate command has the fewest restrictions making it the easiest method to use when terminating a
burst read operation before it has been completed. When the burst terminate command is issued during a burst read cycle, the
pair of data and DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the
mode register. The burst terminate command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
01
2
3
4
5
67
8
CO M M A N D
RE AD A
NO P
NOP
NO P
NOP
NOP
NO P
NO P
Burst
Terminate
CL K
CL K
DQ S
DQ ' s
DOUT 0
Hi -Z
Hi - Z
The burst read ends after a deley equal to the CAS lantency.
DOUT 1
The Burst Terminate command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with auto precharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to
data-mask latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
01
23
4
5
678
CO M M A N D
WR I T E
NO P
NOP
NO P
NOP
N O P
NO P
NO P
CL K
CL K
NO P
DQ S
DQ ' s
t DQ S S
DM
D IN 0
Hi -Z
Hi - Z
ma s k ed b y D M =H
D IN 1 D IN 2 D IN 3 D IN 4 D IN 5 D IN 6 D IN 7
t DS t DH


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