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M13L2561616A-2A Datasheet(PDF) 22 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
22/49
Write Interrupted by a Read & DM
A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one
clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is
registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command
(tWTR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command
is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of
that of write command.
<Burst Length = 8, CAS Latency = 3>
01
23
4
5
678
CO M M A N D
DQ S
DQ ' s
DQ S
DQ ' s
NO P
NO P
NOP
NO P
REA D
NOP
t DQ SS( m a x )
D IN 0
WRITE
t DQS S ( m i n )
DM
CL K
CL K
DM
NOP
NO P
Hi - Z
Hi - Z
t WP R E S
t WT R
*5
Hi -Z
Hi - Z
t WT R
t WP R E S
*5
D IN 1
D IN 2
D IN 3
D IN 4 D IN 5
D IN 6
D IN 7
DOUT0 DOUT1
DOUT0 DOUT1
D IN 0 D IN 1
D IN 2
D IN 3
D IN 4 D IN 5
D IN 6
D IN 7
The following functionality established how a Read command may interrupt a Write burst and which input data is not written into
the memory.
1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where
the Write to Read delay is 1 clock cycle is disallowed.
2. For read commands interrupting a Write burst, the DM pin must be used to mask the input data words which immediately
precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation.
3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory
controller) in time to allow the buses to turn around before the SDRAM drives them during a read operation.
4. If input Write data is masked by the Read command, the DQS inputs are ignored by the DDR SDRAM.
5. Refer to “Burst write operation”


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