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M13L2561616A-2A Datasheet(PDF) 19 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
19/49
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read
command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this
point the data from the interrupting Read command appears. Read to Read interval is tCCD(min).
<Burst Length = 4,
CAS Latency = 3>
Read Interrupted by a Write & Burst Terminate
To interrupt a burst read with a write command, Burst Terminate command must be asserted to avoid data contention on the I/O
bus by placing the DQ’s (Output drivers) in a high impedance state. To insure the DQ’s are tri-stated one cycle before the
beginning the write operation, Burt stop command must be applied at least RU(CL) clocks [RU mean round up to the nearest
integer] before the Write command.
<Burst Length = 4,
CAS Latency = 3>
01
23
4
5
6
7
8
CO M M A N D
DQS
DQ' s
RE A D
NOP
NO P
NO P
NO P
NO P
DOUT 0
Bur s t
Te r m i nate
DIN 0
DOUT 1
DIN 1
DIN 2
DIN 3
CL K
CL K
NO P
W R I T E
The following functionality establishes how a Write command may interrupt a Read burst.
1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate
the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a
Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer].
2. It is illegal for a Write and Burst Terminate command to interrupt a Read with auto precharge command.
01
2
3
4
5
67
8
C O MMA N D
DQ S
DQ ' s
RE A D A
NO P
NO P
NO P
NOP
NOP
NO P
N O P
D OUT A0
R EAD B
DOUT A1
DOUT B2 D OUT B3
D OUT B0 D OUT B 1
CL K
CL K
t CCD( m i n)
Hi - Z
Hi- Z


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