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M13L2561616A-2A Datasheet(PDF) 12 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp
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M13L2561616A-2A Datasheet(HTML) 12 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
12/49
Command Truth Table
COMMAND
CKEn-1 CKEn CS RAS CAS
WE
DM
BA0,
BA1
A10/AP
A12~A11,
A9~A0
Note
Register
Extended MRS
H
X
L
L
L
L
X
OP CODE
1,2
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Auto Refresh
H
3
Entry
H
L
L
L
L
H
X
X
3
L
H
H
H
3
Refresh
Self Refresh
Exit
L
H
H
X
X
X
XX
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Auto Precharge Disable
L
4
Read &
Column
Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
H
Column
Address
(A0~A8)
4
Auto Precharge Disable
L
4,8
Write &
Column
Address
Auto Precharge Enable
H
X
L
H
L
L
V
V
H
Column
Address
(A0~A8)
4,6,8
Burst Terminate
H
X
L
H
H
L
X
X
7
Bank Selection
V
L
Precharge
All Banks
H
X
L
L
H
L
X
X
H
X
5
H
X
X
X
Entry
H
L
L
H
H
H
X
Active Power Down Mode
Exit
L
H
X
X
X
X
X
X
H
X
X
X
Entry
H
L
L
H
H
H
X
H
X
X
X
Precharge Power Down
Mode
Exit
L
H
L
H
H
H
X
X
Deselect (NOP)
H
X
X
X
No Operation (NOP)
H
X
L
H
H
H
XX
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Notes:
1. OP Code: Operand Code. A0~A12 & BA0~BA1: Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A10/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst Terminate command is valid at every burst length.
8. DM and Data-in are sampled at the rising and falling edges of the DQS. Data-in byte are masked if the corresponding
and coincident DM is “High”. (Write DM latency is 0).


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