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M13L2561616A-2A Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L2561616A-2A
Description  Double-data-rate architecture, two data transfers per clock cycle
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Maker  ESMT [Elite Semiconductor Memory Technology Inc.]
Homepage  http://www.esmt.com.tw/index.asp

M13L2561616A-2A Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc.

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M13L2561616A (2A)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2012
Revision : 1.0
AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the
range between VIL(AC) and VIH(AC).
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤
0.2VDDQ is recognized as LOW.
Enables on-chip refresh and address counters.
IDD specifications are tested after the device is properly initialized.
The CLK/ CLK input reference level (for timing referenced to CLK/ CLK ) is the point at which CLK and CLK cross;
the input reference level for signals other than CLK/ CLK , is VREF.
The output timing reference voltage level is VTT.
10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level but specify when the device output is no longer driving (tHZ), or begins driving
11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending
on tDQSS.
13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
14. For command/address input slew rate ≥ 1.0 V/ns
15. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
16. For CLK & CLK slew rate ≥ 1.0 V/ns
17. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
18. Slew Rate is measured between VOH(AC) and VOL(AC).
19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are =
50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to
crosstalk (tJIT(crosstalk)) into the clock traces.
20. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts
for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition
followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
21. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers
for any given cycle.
22. For each of the terms above, if not already an integer, round to the next highest integer.

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