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M13L32321A-2G Datasheet(PDF) 9 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L32321A-2G
Description  Double-data-rate architecture, two data transfers per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M13L32321A-2G Datasheet(HTML) 9 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L32321A (2G)
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
9/48
AC Timing Parameter & Specifications (Note: 1~5, 8~9)
-5
-6
-7.5
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
CL2
7.5
12
7.5
12
7.5
12
CL2.5
6.0
12
6.0
12
7.5
12
Clock Period
CL3
tCK
5.0
12
6.0
12
7.5
12
ns
DQ output access time from
CLK/ CLK
tAC
-0.7
+0.7
-0.7
+0.7
-0.75
+0.75
ns
CLK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS output access time from
CLK/ CLK
tDQSCK
-0.7
+0.7
-0.7
+0.7
-0.75
+0.75
ns
Clock to first rising edge of DQS delay
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQ and DM input setup time (to DQS)
tDS
0.5
0.5
0.5
ns
DQ and DM input hold time (to DQS)
tDH
0.5
0.5
0.5
ns
DQ and DM input pulse width (for
each input)
tDIPW
1.75
1.75
1.75
ns
17
Address and Control Input setup time
(fast slew rate)
tIS
1.0
1.0
1.1
ns
14, 16~18
Address and Control Input hold time
(fast slew rate)
tIH
1.0
1.0
1.1
ns
14, 16~18
Address and Control Input setup time
(slow slew rate)
tIS
1.1
1.1
1.2
ns
15~18
Address and Control Input hold time
(slow slew rate)
tIH
1.1
1.1
1.2
ns
15~18
Control and Address input pulse width
(for each input)
tIPW
2.2
2.2
2.2
ns
17
DQS input high pulse width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS input low pulse width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS falling edge to CLK setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge hold time from CLK
tDSH
0.2
0.2
0.2
tCK
Data strobe edge to output data edge
tDQSQ
0.4
0.45
0.5
ns
21
Data-out high-impedance time from
CLK/ CLK
tHZ
+0.7
+0.7
+0.75
ns
10
Data-out low-impedance time from
CLK/ CLK
tLZ
-0.7
+0.7
-0.7
+0.7
-0.7
+0.7
ns
10
Clock half period
tHP
tCLmin
or
tCHmin
tCLmin
or
tCHmin
tCLmin
or
tCHmin
ns
19~20
DQ-DQS output hold time from DQS
tQH
tHP-
tQHS
tHP-
tQHS
tHP-
tQHS
ns
20
Data hold skew factor
tQHS
0.5
0.5
0.75
ns


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