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M13L32321A-2G Datasheet(PDF) 30 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L32321A-2G
Description  Double-data-rate architecture, two data transfers per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L32321A (2G)
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
30/48
Notes:
1.
This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSNR or tXSRD has been met (if the previous state
was self refresh).
2.
This table is bank - specific, except where noted, i.e., the current state is for a specific bank and the commands shown are
those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3.
Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCDRD or tRCDWR has been met. No data bursts/accesses and
no register accesses are in progress.
Read / Write: A READ / WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet
terminated or been terminated.
Read / Write with Auto Precharge Enabled: See following text, notes 3a, 3b:
3a. For devices which do not support the optional “concurrent auto precharge” feature, the Read with Auto
Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the
access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if
the same burst was executed with Auto Precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the
precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access
period starts with registration of the command and ends where the precharge period (or tRP) begins. During
the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states,
ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the access
period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other
related limitations apply (e.g., contention between READ data and WRITE data must be avoided).
3b. For devices which do support the optional “concurrent auto precharge” feature, a read with auto precharge
enabled, or a write with auto precharge enabled, may be followed by any command to the other banks, as
long as that command does not interrupt the read or write data transfer, and all other related limitations apply
(e.g., contention between READ data and WRITE data must be avoided.)
4.
The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable
commands to the other bank are determined by its current state and Truth Table.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the
bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCDRD or tRCDWR is met. Once tRCDRD
or tRCDWR is met, the bank will be in the ”row active” state.
Read/ Write with Auto -
Precharge Enabled: Starts with registration of a READ / WRITE command with AUTO PRECHARGE enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
5.
The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied
on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRFC is met, the DDR SDRAM will be in the ”all banks idle” state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has
been met. Once tMRD is met, the DDR SDRAM will be in the ”all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
6.
All states and sequences not shown are illegal or reserved.
7.
Not bank - specific; requires that all banks are idle and no bursts are in progress.
8.
May or may not be bank - specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9.
Not bank - specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with AUTO PRECHARGE enabled and
Reads or Writes with AUTO PRECHARGE disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst Terminate must be used to
end the READ prior to asserting a WRITE command,
13. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM
must be powered down and then restarted through the specified initialization sequence before normal operation can
continue.
14. AUTO REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.
15. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state
only.


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