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M13L32321A-2G Datasheet(PDF) 16 Page - Elite Semiconductor Memory Technology Inc.

Part No. M13L32321A-2G
Description  Double-data-rate architecture, two data transfers per clock cycle
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

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ESMT
M13L32321A (2G)
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2012
Revision : 1.0
16/48
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1, A0)
Sequential Mode
Interleave Mode
xx0
0, 1
0, 1
2
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
4
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
8
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to
normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the
DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be
issued.
Output Drive Strength
The device support full drive strength and reduced drive strength options, intended for lighter load and/or point-to-point
environments.
Mode Register
01
234
56
7
CO M M A N D
t CK
P r ec har ge
Al l B an k s
MR S / E M R S
t RP
*2
*1
CL K
CL K
An y
C o mm and
t MRD
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS/EMRS command.


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